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august 1, 2000 1 MIC74 MIC74 micrel MIC74 2-wire serial i/o expander and fan controller advance information general description the MIC74 is a fully programmable serial-to-parallel i/o expander compatible with the smbus? (system manage- ment bus) protocol. it acts as a slave on the bus, providing eight independent i/o lines. each i/o bit can be individually programmed as an input or output. if programmed as an output, each i/o bit can be programmed as an open-drain or complementary push-pull output. if desired, the four most significant i/o bits can be programmed to implement fan speed control. an internal clock generator and state machine eliminate the overhead generally associated with bit-banging fan speed control. programming the device and reading/writing the i/o bits is accomplished using seven internal registers. all registers can be read by the host. output bits are capable of directly driving high-current loads such as leds. a separate interrupt output can notify the host of state changes on the input bits without requiring the MIC74 to perform a transaction on the serial bus or be polled by the host. three address selection inputs are provided, allowing up to eight devices to share the same bus and provide a total of 64 bits of i/o. the MIC74 is available in an ultra-small-footprint 16-lead qsop. low quiescent current, small footprint, and low pack- age height make the MIC74 ideal for portable and desktop applications. typical application r1 led1 led8 r9 r2 r3 r4 r5 r6 r7 r8 3.0v 3.0v vdd /alert data clk alert data clk a0 a1 a2 gnd p0 p1 p2 p3 p4 p5 p6 p7 MIC74 serial-bus-controlled led annunciator features ? provides eight bits of general purpose i/o ? built in fan speed control logic (optional) ? 2-wire smbus ? /i 2 c ? compatible serial interface plus interrupt output ? 2.7v to 3.6v operating voltage range ? 5v-tolerant i/o ? low quiescent current: 2 a (typical) ? bit-programmable i/o options: input or output push-pull or open-drain output interrupt on input changes ? outputs can directly drive leds (10ma i ol ) ? up to 8 devices per bus applications ? general purpose i/o expansion via serial bus ? personal computer system management ? distributed sensing and control ? microcontroller i/o expansion ? fan control ordering information part number temperature range package MIC74bqs C 40 c to +85 c 16-lead qsop micrel, inc. ? 1849 fortune drive ? san jose, ca 95131 ? usa ? tel + 1 (408) 944-0800 ? fax + 1 (408) 944-0970 ? http://www.mic rel.com smbus ? is a trademark of intel corporation. i 2 c ? is a trademark of phillips electronics n.v.
MIC74 micrel MIC74 2 august 1, 2000 pin description pin number pin name pin function 1 C 3a0 C a2 address (input): slave address selection inputs; sets the three least signifi- cant bits of the MIC74 s slave address. 4 C 7p0 C p3 parallel i/o (input/output): general-purpose i/o pin. direction and output type are user programmable. 8 gnd ground 9 C 12 p4 C p7 (/shdn, /fs0 C /fs2) parallel i/o (input/output): p4 C p7 are general-purpose i/o pins. direction and output type are user programmable. shutdown (output): when the fan bit is set, pin 9 becomes shdn. fan speed (output): when the fan bit is set, pins 10 through 12 become / fs0 C /fs2 respectively, controlled by the fan_speed register. 13 /alert interrupt (output): active-low, open-drain output signals input-change- interrupts to the host on this pin. signal is cleared when the bus master (host) polls the ara (alert response address = 0001 100) or reads status. 14 clk serial bus clock (input): the host provides the serial bit clock in this input. 15 data serial data (input/output): serial data input and open-drain serial data output. 16 vdd power supply (input.) pin configuration 1 a0 a1 a2 p0 p1 p2 p3 gnd 16 vdd data clk /alert p7 (/fs2) p6 (/fs1) p5 (/fs0) p4 (/shdn0) 15 14 13 12 11 10 9 2 3 4 5 6 7 8 16-lead qsop
august 1, 2000 3 MIC74 MIC74 micrel absolute maximum ratings (note 1) supply voltage (v dd ) ................................................. +4.6v input voltage [all pins except v dd and gnd] (v in ) ........................ gnd C 0.3v to 5.5v junction temperature (t j ) ...................................... +150 c lead temperature (10 sec.) .................................... +260 c esd rating, note 3 v dd ........................................................................................... 1.5kv a0,a1,a2 ................................................................. 500v others ..................................................................... 200v operating ratings (note 2) supply voltage (v dd ) .................................. +2.7v to +3.6v ambient temperature (t a ) ......................... C 40 c to +85 c package thermal resistance ............................... 163 c/w electrical characteristics 2.7v v dd 3.6v; t a = 25 c, bold values indicate C 40 c t a +85 c; unless noted. symbol parameter condition min typ max units v in input voltage, any pin except gnd C 0.3 5.5 v v dd and gnd i dd operating supply current p[7:0] inputs; p[7:0] = v dd or gnd 2 6 a /alert open; f clk = 100khz i start fan startup supply current during t start ; /alert, /shdn, 1.75 ma (fan mode only) /fs2[2:0] = open; v smbclk = v smbdata = v dd ; p[3:0] = inputs i stby standby supply current /alert = open, v smbclk = v smbdata = v dd ;13 a p[3:0] = inputs serial i/o (data, clk) v il input low voltage C0.3 0.8 v v ih input high voltage 2.0 5.5 v v ol output low voltage i ol = 3ma 0.4 v i leak leakage current v in = 5.5v or gnd C 1+1 a c in input capacitance 10 pf parallel i/o [p0Cp3, p4(/shdn), p5(/fs0)Cp7(/fs2)] v il input low voltage C0.5 0.8 v v ih input high voltage 2 5.5 v i ol output low current v ol = 0.4v, v dd = 2.7v 7 ma v ol = 1v, v dd = 3.3v 10 ma i oh output high current v oh = 2.4v 7 ma i leak leakage current v in = 5.5v or gnd C 1+1 a c in input capacitance 10 pf c out output capacitance 10 pf address input (a0Ca2) v il input low voltage C0.3 0.3v dd v v ih input high voltage 0.7v dd v dd +0.3 v i leak leakage current v in = v dd or gnd C 250 +250 na
MIC74 micrel MIC74 4 august 1, 2000 symbol parameter condition min typ max units /alert v ol output low voltage i ol = 1ma 0.4 v i leak leakage current v in = v dd or v ss C 1 250 +1 a ac characteristics t start fan startup interval normal operation 0.5 1 3.3 sec t pulse minimum pulse-width minimum pulse-width on p n to 10 ns generate an interrupt, note 7 t /int interrupt delay interrupt delay from state change 4 s on p n to /alert v ol , note 7 t /ir delay from status read or ara 4 s response to /alert v oh t hd:sta hold time, note 7 hold time after repeated start condition. 4.0 s after this period, the first clock is generated. t su:sta setup time, note 7 repeated start condition setup time 4.7 s t su:sto stop condition setup time note 7 4.0 s t hd:dat data hold time note 7 500 ns t su:dat data setup time note 7 0ns t timeout clock low time-out notes 4, 7 25 35 ms t low clock low period notes 5, 7 4.7 s t high clock high period notes 5, 7 4.0 50 s t f clock/data fall time notes 6, 7 300 ns t r clock/data rise time notes 6, 7 1000 ns t buf bus free time between stop and note 7 4.7 s start condition note 1. exceeding the absolute maximum rating may damage the device. note 2. the device is not guaranteed to function outside its operating rating. note 3. devices are esd sensitive. handling precautions recommended. human body model, 1.5k in series with 100pf. note 4. devices participating in a transfer will timeout when any clock low exceeds the value of t timeout(min) of 25ms. devices that have detected a timeout condition must reset the communication no later than t timeout(max) of 35ms. the maximum value specified must be adhered to by both a master and a slave as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms). note 5. t high(max) provides a simple guaranteed method for devices to detect bus idle conditions. note 6. rise and fall time is defined as follows: t r = v il(max) C 0.15v to v ih(min) + 0.15v; t f = 0.9v dd to v il(max) C 0.15v. note 7. guaranteed by design. timing definitions data clk t r t f t hd:sta t su:sto t hd:dat t hd:sta t su:dat t high t su:sta t buf t low sto p sto p s tart s tart
august 1, 2000 5 MIC74 MIC74 micrel register descriptions device configuration register g f c _ v e d ] 7 [ d] 6 [ d] 5 [ d] 4 [ d] 3 [ d] 2 [ d] 1 [ d] 0 [ d . o r e z s a e t i r w s y a w l an a fe i power-on default value: 0000 0000 b , 00 h interrupts disabled not in fan mode command_byte addess: 0000 0000 b , 00 h type: 8-bits, read/write bit name: ie function: global interrupt enable. operation: 1 = enabled 0 = disabled bit name: fan function: selects fan mode (p[7:4] vs. /fs[2:0], /shdn) operation: 1 = fan mode 0 = i/o mode bit name: d[2] through d[6] function: reserved operation: reserved always write as zero data direction register r i d ] 7 [ d] 6 [ d] 5 [ d] 4 [ d] 3 [ d] 2 [ d] 1 [ d] 0 [ d 7 r i d6 r i d5 r i d4 r i d3 r i d2 r i d1 r i d0 r i d power-on default value: 0000 0000 b , 00 h all p n s configured as inputs command_byte addess: 0000 0001 b , 01 h type: 8-bits, read/write bit name: dir n function: selects data direction, input or output, of p n operation: 1 = output 0 = input notes: if fan mode is selected, that is, the fan bit of the dev_cfg register is set to one, p[7:4] are automatically configured as open-drain outputs. they are then referred to as /fs[2:0] and /shdn. the dir register has no effect on these i/o bits while in fan mode. output configuration register g f c _ t u o ] 7 [ d] 6 [ d] 5 [ d] 4 [ d] 3 [ d] 2 [ d] 1 [ d] 0 [ d 7 t u o6 t u o5 t u o4 t u o3 t u o2 t u o1 t u o0 t u o power-on default value: 0000 0000 b , 00 h all outputs open-drain command_byte addess: 0000 0010 b , 02 h type: 8-bits, read/write bit name: out n function: selects output driver configuration of p n when p n is configured as an output. operation: 1 = push-pull 0 = open-drain notes: if fan mode is selected, that is, the fan bit of the dev_cfg register is set to one, p[7:4] are automatically configured as open-drain outputs. they are then referred to as /fs[2:0] and /shdn. the out_cfg register has no effect on these i/o bits while in fan mode. status register s u t a t s ] 7 [ d] 6 [ d] 5 [ d] 4 [ d] 3 [ d] 2 [ d] 1 [ d] 0 [ d 7 s6 s5 s4 s3 s2 s1 s0 s power-on default value: 0000 0000 b , 00 h no interrupts pending command_byte addess: 0000 0011 b , 03 h type: 8-bits, read only bit name: s n function: flag for pn input-change event when p n is configured as an input; s n is set when the corresponding input changes state. operation: 1 = change occured 0 = no change occured notes: if fan mode is selected, that is, the fan bit of the dev_cfg register is set to one, p[7:4] are automatically configured as open-drain outputs. they are then referred to as /fs[2:0] and /shdn. no interrupts of any kind are generated by these pins while in fan mode. all status bits are cleared after any read operation is performed on status.
MIC74 micrel MIC74 6 august 1, 2000 data register a t a d ] 7 [ d] 6 [ d] 5 [ d] 4 [ d] 3 [ d] 2 [ d] 1 [ d] 0 [ d 7 p6 p5 p4 p3 p2 p1 p0 p power-on default value: 1111 1111 b , ff h command_byte addess: 0000 0101 b , 05 h type: 8-bits, read/write bit name: p n function: returns the current state of any p n configured as an input and the last value written to p n s configured as outputs; writing the data register sets the output state of any p n s configured as outputs; writes to i/o bits configured as inputs are ignored. read operation: 1 = p n is high 0 = p n is low write operation: 1 = p n is set to one 0 = p n is cleared notes: if fan mode is selected, that is, the fan bit of the dev_cfg register is set to one, p[7:4] are automatically configured as open-drain outputs. they are then referred to as /fs[2:0] and /shdn. the state of these pins is deter- mined by the fan_speed register. while in fan mode, d[7:4] of the data registers have no effect. fan speed register d e e p s _ n a f ] 7 [ d] 6 [ d] 5 [ d] 4 [ d] 3 [ d] 2 [ d] 1 [ d] 0 [ d . o r e z s a e t i r w s y a w l ad e e p s n a f power-on default value: 0000 0000 b , 00 h fan off command_byte addess: 0000 0110 b , 06 h type: 8-bits, read/write bit name: d[0] through d[2] function: determines bit-pattern on fs[2:0] operation: ] 0 : 2 [ d e u l a v e t a t s t u p t u o d e e p s n a f ] 0 : 2 [ s f /n d h s / 0 0 01 1 10 f f o 1 0 00 1 11 ) t s e w o l s ( 1 d e e p s 0 1 01 0 11 2 d e e p s 1 1 00 0 11 3 d e e p s 0 0 11 1 01 4 d e e p s 1 0 10 1 01 5 d e e p s 0 1 11 0 01 6 d e e p s 1 1 10 0 01 ) t s e t s a f ( 7 d e e p s fan speed settings notes: any time the fan speed register contains zero, that is, the fan is shut down, and a non-zero value is written into the fan speed register, the /fs[2:0] and /shdn outputs will assume the highest fan speed state for approximately one second (t start ). following this interval, the state of the fan speed control outputs will assume the value indicated by the contents of fan_speed. this insures that the fan will start reliably when low speed operation is desired. bit name: d[3] through d[7] function: reserved operation: always write as zero. interrupt mask register k s a m _ t n i ] 7 [ d] 6 [ d] 5 [ d] 4 [ d] 3 [ d] 2 [ d] 1 [ d] 0 [ d 7 m i6 m i5 m i4 m i3 m i2 m i1 m i0 m i power-on default value: 0000 0000 b , 00 h command_byte addess: 0000 0100 b , 04 h type: 8-bits, read/write bit name: im n function: interrupt enable bit for p n when p n is config- ured as an input operation: 1 = enabled 0 = disabled notes: if fan mode is selected, that is, the fan bit of the dev_cfg register is set to one, p[7:4] are automatically configured as open-drain outputs. they are then referred to as /fs[2:0] and /shdn. no interrupts of any kind are generated by these pins while in fan mode.
august 1, 2000 7 MIC74 MIC74 micrel functional description pin descriptions vdd power supply input connection. see operating ratings. gnd ground or return connection for all MIC74 functions. clk an clk signal is provided by the host (master) and is common to all devices on the bus. the clk signal controls all transactions in both directions on the bus and is applied to each MIC74 at the clk pin. data serial data is bidirectional and is common to all devices on the bus. the MIC74 s data output is open-drain. the data line requires one external pull-up resistor or current source per system that can be located anywhere along the line. a2, a1, a0 an MIC74 responds to its own unique address which is assigned using the a0 C a2 pins. a0 C a2 set the three lsbs (least significant bits) of the MIC74 s 7-bit slave address. the three address pins allow eight unique MIC74 addresses in a system. when the MIC74 s address matches an address received in the serial bit stream, communication is initiated. a2, a1 and a0 should be connected to gnd or v dd . the state of these pins is sampled only once at device power-on. new slave addresses are not accepted unless the MIC74 is powered off then on. functional diagram gnd v dd p n (typical i/o port) s q qr edge detect int n im n status n status_read n data n (input) out_cfg n dir n data n (output) typical i/o port (fan speed control logic not shown) s t u p n is s e r d d a e v a l s 4 7 c i m 2 a1 a0 ay r a n i bx e h 000 0 0 1 0 0 0 0 b 0 2 h 001 0 0 1 0 1 0 0 b 1 2 h 010 0 0 1 0 0 1 0 b 2 2 h 011 0 0 1 0 1 1 0 b 3 2 h 100 0 0 1 0 0 0 1 b 4 2 h 101 0 0 1 0 1 0 1 b 5 2 h 110 0 0 1 0 0 1 1 b 6 2 h 111 0 0 1 0 1 1 1 b 7 2 h table 1. MIC74 address configuration alert response address the MIC74 also responds to the ara (alert response address). the ara is used by the master (host) to request the address of a slave that has provided an interrupt to the master via the /alert line. the ara is a single address (0001 100) common to all slaves and is described in more detail under interrupt generation with related information under /alert. also see figure 7. p n , /shdn, and /fs0 C /fs2 p0 through p7 are general-purpose input/output bits. each bit is independently programmable as an input or an output. if programmed as an output, each bit is further programmable as either a complementary push-pull or open-drain output. if properly enabled, any p n programmed as an input will generate an interrupt to the host using the /alert output when the input changes state. in this way, the MIC74 can
MIC74 micrel MIC74 8 august 1, 2000 notify the host of an input change without requiring periodic polling by the host or a message transaction on the bus. regardless of whether interrupts are enabled or disabled, each input-change event also sets the corresponding bit in the status register. i/o configuration is performed using the output configuration (out_cfg), i/o direction (dir), and interrupt mask (int_mask) registers. if the fan bit in the device configuration register is set, the states of p[7:4] are controlled by the fan_speed register. the bits in the out_cfg, dir, and int_mask registers corresponding to p[7:4] are ignored. when in fan mode, p[7:4] are referred to as /fs2, /fs1, /fs0, and /shdn. while in this mode, no interrupts of any kind will be generated by these pins. /alert the alert signal is an open-drain, active-low output. the operation of the /alert output is controlled by the im n bits in the int_mask register and the global interrupt enable bit (ie) in the dev_cfg register. if the ie bit is set to zero, or if the corresponding interrupt enable bit, im n , is set to zero, no input-change interrupts will be generated. (regardless of the ie bit setting, the change will be reflected in the status register.) if the ie bit is set to one, im n is set to one, and p n is an input, then /alert is driven active whenever p n changes state, (goes from a high-to-low or low-to-high state). once triggered, /alert is unconditionaly reset to its inactive state once the MIC74 successfully responds to the alert response address or status is read. serial port operation the MIC74 uses standard smbus read_byte and write_byte operations to communicate with its host. the read_byte operation is a composite read-write opera- tion consisting of first sending the MIC74 s slave address followed by a command byte (a write) and then resending the slave address and clocking out the data byte (a read). the command byte is the address of the target register. see table 2. an example of a read_byte operation is shown in figure 8. similarly, the write-byte operation consists of sending the device s slave address followed by a command byte and the byte to be written to the target register. again, in the case of the MIC74, the command byte is the address of the target register. see table 2. in addition, to the read byte and write byte protocols, the MIC74 adheres to the smbus protocol for response to the ara (alert response address). an MIC74 expects to be interrogated using the ara when it has asserted its /alert output. /alert interrupts can be enabled or disabled using the ie bit in the dev_cfg register. power-on when power is initially applied, the MIC74 s internal registers will assume their power-up default state and the state of the address inputs, a2, a1 and a0, will be read to establish the device s slave address. see the individual register descrip- tions for each registers default state. also see table 2. i/o ports each i/o bit, p0 through p7, may be individually programmed as an input or output using the corresponding bit in the i/o direction register, dir. if programmed as an output, each is further programmable as either a complementary push-pull or open-drain output using the output configuration register, out_cfg. if enabled by the corresponding bit, im n , in the interrupt mask register int_mask, each p n programmed as an input will generate an interrupt to the host on /alert if the input changes state. in this way, the MIC74 can notify the host of an input change without requiring periodic polling by the host or a transaction on the bus. each input-change event also sets the corresponding bit in the status register, status. see functional diagram for the logic arrangement of a typical MIC74 i/o port. fan speed control if the fan bit in the device configuration register is set, the state of p[7:4] is controlled by the fan_speed register. the bits in the out_cfg, dir, and int_mask registers corre- sponding to p[7:4] are ignored. when in fan control mode, p[7:4] are referred to as /fs2, /fs1, /fs0, and /shdn. while in this mode, no interrupts of any kind will be generated by these pins. see applications information for typical fan speed control applications. r e t s i g e r e m a n r e t s i g e r n o i t p i r c s e d s s e r d d a e l b a l i a v a s n o i t a r e p o t l u a f e d n o - r e w o p y r a n i bx e hy r a n i bx e h g i f n o c _ v e dn o i t a r u g i f n o c e c i v e d0 0 0 0 0 0 0 0 b 0 0 h e t i r w / d a e r t i b - 80 0 0 0 0 0 0 0 b 0 0 h r i dn o i t c e r i d o / i1 0 0 0 0 0 0 0 b 1 0 h e t i r w / d a e r t i b - 80 0 0 0 0 0 0 0 b 0 0 h g f c _ t u on o i t a r u g i f n o c t u p t u o0 1 0 0 0 0 0 0 b 2 0 h e t i r w / d a e r t i b - 80 0 0 0 0 0 0 0 b 0 0 h s u t a t ss u t a t s t p u r r e t n i1 1 0 0 0 0 0 0 b 3 0 h d a e r t i b - 80 0 0 0 0 0 0 0 b 0 0 h k s a m _ t n ik s a m t p u r r e t n i0 0 1 0 0 0 0 0 b 4 0 h e t i r w / d a e r t i b - 80 0 0 0 0 0 0 0 b 0 0 h a t a do / i e s o p r u p - l a r e n e g1 0 1 0 0 0 0 0 b 5 0 h e t i r w / d a e r t i b - 81 1 1 1 1 1 1 1 b f f h d e e p s _ n a fd e e p s n a f0 1 1 0 0 0 0 0 b 6 0 h e t i r w / d a e r t i b - 80 0 0 0 0 0 0 0 b 0 0 h table 2. register summary
august 1, 2000 9 MIC74 MIC74 micrel fan start-up any time the fan speed register contains zero (fan is off) and then a nonzero value is written to fan_speed, the /fs[2:0] and /shdn outputs will assume the highest fan speed state for approximately one second (t start ). following this inter- val, the state of the fan speed control outputs will assume the value indicated by the contents of fan_speed. this insures that the fan will start reliably when low speed operation is desired. the t start interval is generated by an internal oscillator and counters. at the end of t start , this oscillator is powered down to reduce overall power consumption. MIC74 vin /shdn gnd vout fb r f2 r pull-up /fs2 r f2 /fs1 r f2 r min_speed /fs0 /shdn fan r fb regulator figure 1. fan speed control application proper sequencing of the /fs[2:0] and /shdn signals is performed by the MIC74 s internal logic state machine. when activating the fan from the off state, the /fs[2:0] lines change state first, then, after a delay equal to one-half of t start , the /shdn pin is deasserted. conversely, when the fan is shut down (zero is written to fan_speed), the /shdn pin is de- asserted first. the /fs[2:0] lines are subsequently deasserted after a delay of 1 ? 2 t start . the internal oscillator is also powered down following the t start /2 interval at fan shut- down. these timing relationships are illustrated in figure 2. interrupt generation assuming that any or all of the i/o s are configured as inputs, the MIC74 will reflect the occurrence of an input change in the corresponding bit in the status register, status. this action cannot be masked. an input change will only generate an interrupt to the host if interrupts are properly configured and enabled. the MIC74 can operate in either polled mode or interrupt mode. in the case of polled operation, the host periodically reads the contents of status to determine the device state. the act of reading status clears its contents. repeating events which have occurred since the last read from status will not be discernable to the host. interrupts are only generated if the global interrupt enable bit, ie, in the dev_cfg register is set. the /alert signal will be asserted (driven low) when an interrupt is generated. the MIC74 expects to be interrogated using the ara when it has generated an interrupt output. once it has successfully responded to the ara (alert response address), the /alert output will be deasserted. the contents of the status register will not be cleared until it is read using a read byte operation. if a given system does not wish to use the smbus ara protocol for reporting interrupts, the system may simply poll the contents of the status register after detecting an interrupt on /alert. this action will clear the contents of status and cause /alert to be deasserted. reading the status register is an acceptable substitute for using the ara protocol. presumably, however, it will involve higher system overhead since all the devices on the bus must be polled to determine which one generated the interrupt. /fs2 value written to fan_speed (00 h ) /fs0 /shdn /fs1 t start /2 t start /2 t start shutdown shutdown 01 h 07 h 01 h 02 h 05 h 00 h fan supply output voltage* fan rotation speed* * fan supply output voltage and speed are not to scale. figure 2. typical MIC74 fan-mode timing and system behavior
MIC74 micrel MIC74 10 august 1, 2000 applications information bit transfer the data received on the data pin must be stable during the high period of the clock. data clk data change allowed data stable, data valid figure 3. acceptable bit transfer conditions data can change state only when the clk line is low. refer to figure 3. start and stop conditions two unique bus situations define start and stop condi- tions. a high-to-low transition of the data line while clk is high indicates a start condition. a low-to-high transition of the data line while clk is high defines a stop condition. see figure 4. data clk s tart sto p figure 4. start and stop definitions start ( s ) and stop ( p ) conditions are always generated by the bus master (host). after a start condition, the bus is consid- ered to be busy. the bus becomes free again after a certain time following a stop condition or after both clk and data lines remain high for more than 50 s. serial byte format every byte consists of 8 bits. each byte transferred on the bus must be followed by an acknowledge bit. bytes are trans- ferred with the msb (most significant bit) first. see figure 5. acknowledge and not acknowlege the acknowledge related clock pulse is generated by the master. the transmitter releases the data line (high) during the acknowledge clock cycle. in order to acknowledge (ack) a byte, the receiver must pull the data line low during the high period of the clock pulse according the bus timing specifications. a slave device that wishes to not acknowledge a byte must let the data line remain high during the acknowledge clock pulse. see fig- ure 6. 123456789 ack msb lsb nak (high) a ck (low) data (host) clk data (slave MIC74) figure 6. acknowledge and not acknowledge 123456789 123456789 ack ack msb lsb data clk byte complete s tart sto p figure 5. serial byte format
august 1, 2000 11 MIC74 MIC74 micrel s00011001a0100a 2 a 1 a 0 0/ap alert response address (master requests address of interupting device) p0* / alert slave address (interrupting MIC74 announces its address) master-to-slave transmission slave-to-master response stop acknowledge r/w = read not acknowledge t /int t /ir * assumes p0 interrupts properly configured and enabled. p0 used as an example. timing for p1 to p7 is identical. figure 7. interrupt handling using the alert response address /a p s0001a 2 a 1 a 0 0a000000 xxxxxxxx 11a a slave address (host addresses an MIC74) p0* / alert command byte (03 h = selects status register) status value ? (MIC74 sends status) slave address (host addresses an MIC74) master-to-slave transmission slave-to-master response acknowledge r/w = write s0001a 2 a 1 a 0 1 r/w = read stop not acknowledge t /int t /r * assumes p0 interrupts properly configured and enabled. p0 used as an example. timing for p1 to p7 is identical. ? status register is cleared to zero following this operation. acknowledge acknowledge figure 8. interrupt handling without the alert response address
MIC74 micrel MIC74 12 august 1, 2000 initializing the MIC74 the MIC74 s internal registers are reset to their default state at power-on. the MIC74 s default state can be summarized as follows: ? all i/o s configured as inputs (dir = 00 h ) ? output configuration set to open-drain (out_cfg = 00 h ) ? all outputs high/floating (data = ff h ) ? fan functions disabled (fan_speed = 00 h , fan bit of dev_cfg = 0) ? all interrupts masked (ie bit of dev_cfg = 0) the result of this configuration is that all i/o pins will essen- tially float unless driven by external circuitry. any system using the MIC74 will need to initialize the internal registers to the state required for proper system operation. the recom- mended order for initializing the MIC74 s registers is as follows: write desired output values to data set output configuration in out_cfg set desired i/o's as outputs by writing dir set initial fan speed in fan_speed (if using) read status to clear it write dev_cfg to turn on fan (if using) initialize for polling initialization complete figure 9a. initializing the MIC74 for polled operation write desired ouput values to data set output configuration in out_cfg set desired i/o's as outputs by writing dir set initial fan speed in fan_speed (if using) write int_mask to enable interrupts (if using) read status to clear it write dev_cfg to turn on interrupts and fan (if using) initialize for interrupts initialization complete figure9b. initializing the MIC74 for interrupts 1. write data 2. write out_cfg 3. write dir 4. write fan_speed (if using fan mode) 5. write int_mask (if using interrupts) 6. read status to clear it. 7. write dev_cfg to enable fan mode and/or interrupts, if using at the conclusion of step three, any i/o s configured as outputs in step two will be driven to the levels programmed into the data register in step one. the order of step 1 through step 3 is important to insure that spurious data does not appear at the i/o s during configuration. following step 7, programming the device configuration register, the MIC74 will begin generating interrupts if they are enabled, and the fan will be started if fan_speed contains a nonzero value. the corresponding interrupt service routines (if any) must be initialized and enabled prior to step seven. status should be cleared (step 6) in both polled and interrupt driven sys- tems.
august 1, 2000 13 MIC74 MIC74 micrel polled mode input state changes on i/o s configured as inputs will be reflected in the status register regardless of the state of the global interrupt enable bit (ie) and the individual interrupt mask bits in int_mask. in a system utilizing polling to monitor for input changes, the status register is periodically read to check for input events. the act of reading status clears it in preparation for detecting future events. the status bits corresponding to i/o s configured as outputs or corre- sponding to p[7:4] when in fan mode will not be set by state changes on these pins. it is always good practice, however, to mask the value obtained when reading status to elimi- nate any bits, output or otherwise, that are not of immediate concern. this will help avoid problems if software changes are made in the future. the flowchart shown in figure 9a illustrates the steps in- volved in initializing the MIC74 for polled operation. the flowchart in figure 10 illustrates the corresponding polling routine. the process for writing output data is straightfor- ward simply write the desired bit pattern to data. (special precautions may be required when changing output data in an interrupt driven system, however. see the discussion below under writing to the data register. ) interrupt mode input state changes on i/os configured as inputs will be reflected in the status register regardless of the state of the global interrupt enable bit (ie) and the individual interrupt mask bits in int_mask. in a system utilizing interrupts to detect input changes, one or more of the bits in the interrupt mask register, int_mask, are set to allow interrupts on /alert to be generated by input events. the global interrupt enable bit, ie, in the device configuration register must also be set to enable interrupts. the flowchart shown in figure 9b illustrates the steps in- volved in initializing the MIC74 for interrupt-driven operation. the flowchart in figure 11 illustrates the corresponding inter- rupt service routine using the smbus ara (alert response address). the corresponding timing diagram is shown in figure 7. the flowchart in figure 12 illustrates the corre- sponding interrupt service routine using polling to determine the interrupt source. figure 8 illustrates the timing. utilizing the ara greatly speeds identification of the interrupting slave device and lowers latency, as only a single transaction on the bus is necessary to identify the interrupt source. using either method, status must be read to determine the exact source of the interrupt within the MIC74. the act of read status is s x set ? no ye s polling the MIC74 service function x is status 00 h ? ye s no is s m set ? no ye s service function m is s n set ? no ye s service function n figure 10: polling the MIC74
MIC74 micrel MIC74 14 august 1, 2000 read status is s x set ? no ye s polled i.s.r. service function x is status 00 h ? ye s no is s m set ? no ye s service function m is s n set ? no ye s service function n service other devices return from isr figure 12: interrupt service routine without ara reading status clears it in preparation for detecting future events. the status bits corresponding to i/o s configured as outputs or corresponding to p[7:4] when in fan mode will not be set by state changes on these pins. it is always good practice, however, for the interrupt service routine to mask the value obtained when reading status to eliminate any bits, output or otherwise, that are not of immediate concern. this will help avoid problems if software changes are made in the future. the process for writing output data is straightforward simply write the desired bit pattern to data. special precau- tions may be required, however, when changing output data in an interrupt driven system. see the discussion below under writing to the data register. read status to determine source read alert response address interrupts pending ? no ye s is s x set ? no ye s interrupt service routine return from isr service function x is interrupt from MIC74 ye s no service other devices is s m set ? no ye s service function m is s n set ? no ye s service function n figure 11: interrupt service routine using the ara writing to the data register multiple software routines may use the various output bits available on the MIC74 to control individual functions such as power switches, led s, etc. these various functions may be handled by independent software routines which must ma- nipulate individual output bits without regard for other bits. care must be taken to insure that these various software routines do not interfere with each other when modifying output data. the recommended procedure for changing isolated output bits is as follows: 1. read data 2. set desired bits by oring the value read from data with an appropriate mask value 3. clear desired bits by anding the value read from data with an appropriate mask value 4. write the result back to data a functionally equivalent alternative to this procedure is to keep an image of the data register in software. any indepen- dent routines would make changes to this image using the procedure above and then call a routine that actually writes
august 1, 2000 15 MIC74 MIC74 micrel the new image to data. interrupts would be disabled briefly while data is being modified. regardless of which procedure is used, it is important that only one software routine at a time attempts to make changes to the output data. in a system where polling is the exclusive method for servicing inputs, this is usually not a problem. if interrupts are employed to any degree in dealing with MIC74 inputs, care must be taken to insure that a software routine in the midst of making changes to outputs is not interrupted by another routine that proceeds to make its own changes. the risk is that the value in data will be changed by an interrupt- ing routine after it is read by a different routine in the process of making its own changes. if this occurs, the value written to data by the first routine may be incorrect. the most straight- forward solution to this potential problem is to disable system interrupts while the data register is actually being modified. application circuits the MIC74, in conjunction with a linear low-dropout or switching regulator, can be configured as a fan speed control- ler. most adjustable regulators have a feedback pin and use an external resistor divider to adjust the output voltage. the MIC74 is designed to take advantage of this configuration with its ability to manipulate multiple feedback resistors connected to the p4 C p7 outputs. individual open-drain out- put bits are selectively grounded or allowed to float under the control of the internal state machine. this action raises or lowers the equivalent resistance seen in the regulator s feedback path, thus changing the output voltage. any conventional adjustable regulator is usually suitable for use with the MIC74. the output voltage corresponding to each value to be programmed into the fan speed register can be determined by selecting the resistors in the circuit. the regulator itself can be chosen to meet the needs of the application, such as input voltage, output voltage, current handling capability, maximum power dissipation, and physi- cal space constraints. two circuit examples are shown be- low. the circuit of figure 13 illustrates use of a typical ldo linear regulator such as the mic29152. a switching regulator- based fan control circuit using the mic4574 200khz simple 0.5a buck regulator is shown in figure 14. both circuits assume a 12v fan power supply but will accommodate much higher input voltages if required (mic4574: 24v, mic29152: 26v). care must be taken, however, to insure that the maximum power dissipation of the regulator is not exceeded. if the regulator overheats, its internal thermal shutdown circuitry will deactivate it. (see mic29152 or mic4574 datasheet.) since the MIC74 powers up with all its i/o s inputs (floating), both circuits will power-up with the fan running at a minimum speed determined by the value of r min_speed . once the MIC74 s fan mode is activated by setting the appropriate bit MIC74 in en gnd out fb r f2 1k /fs2 r f1 1.8k /fs1 r f0 3.5k r min_speed 1k p3 p2 p1 p0 /fs0 /shdn fan a-speed hp2a-b3 or similar r fb 3k r pu 100k c3 220 f mic29152 c1 10 f c4 0.1 f +12v +3.3v vdd smbclk smbdata smbalert a2 a1 a0 gnd smbus host figure 13. fan speed control using an adjustable low-dropout regulator MIC74 in shdn pgnd sgnd sw fb r f2 1k /fs2 r f1 1.8k /fs1 r f0 3.5k r min_speed 1k p3 p2 p1 p0 /fs0 /shdn fan a-speed hp2a-b3 or similar r fb 3k c2 3300pf 100k r base 150k r pu 200k c3 220 f mic4574 c1 10 f c4 0.1 f +12v +3.3v vdd smbclk smbdata smbalert a2 a1 a0 gnd smbus host +3.3v d1 l1 100 h q1 2n3906 figure 14. fan speed control using a buck converter
MIC74 micrel MIC74 16 august 1, 2000 d e e p s _ n a f e u l a v d e e p s n a f d e t c e l e s r b f r n i m r 2 f r 1 f r 0 f r q e v t u o 0 0 0 0 0 0 0 0 b p u - r e w o pk 3k 1n e p on e p on e p ok 1v 6 9 . 4 0 0 0 0 0 0 0 0 b f f o n a fk 3k 1n e p on e p on e p ok 1v 0 1 0 0 0 0 0 0 0 b t s e w o lk 3k 1n e p on e p ok 6 . 33 8 7v 9 9 . 5 0 1 0 0 0 0 0 0 b t s e w o l d n 2k 3k 1n e p ok 8 . 1n e p o3 4 6v 3 0 . 7 1 1 0 0 0 0 0 0 b t s e w o l d r 3k 3k 1n e p ok 8 . 1k 6 . 35 4 5v 6 0 . 8 0 0 1 0 0 0 0 0 b m u i d e mk 3k 1k 1n e p on e p o0 0 5v 8 6 . 8 1 0 1 0 0 0 0 0 b t s e h g i h d r 3k 3k 1k 1n e p ok 6 . 39 3 4v 1 7 . 9 0 1 1 0 0 0 0 0 b t s e h g i h d n 2k 3k 1k 1k 8 . 1n e p o1 9 3v 5 7 . 0 1 1 1 1 0 0 0 0 0 b t s e h g i hk 3k 1k 1k 8 . 1k 6 . 33 5 3v 8 7 . 1 1 table 3. fan speed selection in the configuration register, the fan will be shutdown by the assertion of the /shdn output if fan_speed is zero. if fan_speed is programmed with any nonzero value, the fan will be driven to its maximum speed for the duration of t start (about 1 second) and then assume the programmed speed. note that the circuit in figure 14 contains an additional transistor, q1, as an inverter because the regulator in this example has an active-high shutdown input rather than an enable input. otherwise the circuits function identically. table 3 lists the output voltages corresponding to all the fan speeds and system states possible with these circuits. the following equations are used to calculate the resistor values used in MIC74 fan speed control circuits. it is assumed here that the regulator s internal reference voltage is 1.24v. if the regulator uses a different reference voltage, that value should be used instead. the following equations show how to calculate the resistor values for the fan controllers. for example, when the fan speed register contains 011 b , which is the 3rd lowest speed, r f1 and r f0 are parallel to r min to give the equivalence resistor (r eq ) value of 545 ? . rrrr eq min = f1 f0 || || r eq = 1.8k 3.6k 1k || || r eq =? 545 the output voltage is calculated by using: v r r out fb eq =+ ? ? ? ? ? ? 1.24v 1 v out =+ ? ? ? ? ? ? ? 1.24v 1 3k 545 v out = 8.06v
august 1, 2000 17 MIC74 MIC74 micrel package information 45 0.2284 (5.801) 0.2240 (5.690) seating plane 0.009 (0.2286) ref 0.012 (0.30) 0.008 (0.20) 0.157 (3.99) 0.150 (3.81) 0.050 (1.27) 0.016 (0.40) 0.0688 (1.748) 0.0532 (1.351) 0.196 (4.98) 0.189 (4.80) 0.025 (0.635) bsc pin 1 dimensions: inches (mm) 0.0098 (0.249) 0.0040 (0.102) 0.0098 (0.249) 0.0075 (0.190) 8 0 16-pin qsop (qs)
MIC74 micrel MIC74 18 august 1, 2000
august 1, 2000 19 MIC74 MIC74 micrel
MIC74 micrel MIC74 20 august 1, 2000 micrel inc. 1849 fortune drive san jose, ca 95131 usa tel + 1 (408) 944-0800 fax + 1 (408) 944-0970 web http://www.micrel.com this information is believed to be accurate and reliable, however no responsibility is assumed by micrel for its use nor for an y infringement of patents or other rights of third parties resulting from its use. no license is granted by implication or otherwise under any patent or pat ent right of micrel inc. ? 2000 micrel incorporated

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